My Homebrew CPU Arch: Leftie-8, Day 2

This is the second catch-up post for the homebrew CPU. All this stuff I worked on a few weeks ago but hadn't gotten around to posting yet.

The Instructions

Leftie-8 Instructions come in 3 categories: Control, Arithmetic, and Branching. As mentioned in the previous post, almost every instruction with several arguments use the A register as the left-hand-side of a binary operation. The general rule is that instructions with 2 arguments, one is A and the other is fetched via some addressing. The addressed argument can be obtained with several addressing modes which are categorized into addressing classes. Instructions with outputs only ever write to the register file except for the dedicated store instruction.

The instruction addressing modes are:

• 8b immediate value
• register value: R0-R7 and A
• zero page indirect with 8b immediate address
• zero page indirect with offset register R0/R1
• zero page indirect with 8b imm + offset register R0/R1
• 16b immediate value
• register|A 16b absolute address indirect
• PC relative +/- 8b immediate
• PC relative +/- A

The addressing classes:

• Class 0: High-use Arithmetic instructions
• 8b imm
• register
• zero page imm
• zero page imm + offset (offset reg only is treated as a sub mode here)
• Class 1: Low-use Arithmetic instructions
• register
• 8b imm
• Class 2: Register only
• register
• Class 3: Implicit (no argument is needed)
• Class 4: Data movement
• register
• zero page 8b imm
• zero page offset reg
• zero page imm + offset
• combined Rx|A address
• 16b imm
• Branching
• PC relative +/- A
• PC relative +/- 8b imm
• Jump
• 16b imm
• combined Rx|A
• PC relative +/- A
• PC relative +/- 8b imm
• JSR
• 16b imm
• quick call register

That's all for now. Next up I'll start listing each instruction and what they do. I could do it all now but wanna break up the CPU stuff with my other projects. Till next time!